1. Field
Example embodiments may relate to a semiconductor test apparatus, for example, to a wafer-type probe card, a method for fabricating a wafer-type probe card, and/or a semiconductor test apparatus having the wafer type probe card.
2. Description of the Related Art
Related art semiconductor devices may be manufactured through a series of semiconductor fabricating processes including a process of fabricating a semiconductor wafer, a process of fabricating a plurality of semiconductor chips on the semiconductor wafer, a process of performing an electrical die sorting (EDS) test on the plurality of semiconductor chips to determine whether the semiconductor chips are, defective, a process of packaging non-defective semiconductor chips, and/or a process of finally testing the packaged semiconductor chips. The EDS test process may determine whether the semiconductor chips formed on the wafer are electrically defective and may use a test apparatus that applies an electrical signal to the semiconductor chips to perform this determination. A related art EDS test apparatus may include a tester generating an electrical signal and/or a probe card including a plurality of needles to transmit the electrical signal to electrodes on semiconductor chips on a semiconductor wafer. The probe card may transmit the electric signal generated by the tester to the wafer through the needles contacting the wafer and/or from the wafer to the tester.
FIG. 1A is a plan view illustrating a related art probe card, and FIG. 1B is a schematic cross-sectional view illustrating the related art probe card of FIG. 1A. As shown in FIGS. 1A and 1B, a related art probe card 10 may include a printed circuit board (PCB) 11 having a penetration hole 15 in the center and/or a plurality of probe pins 13 attached on a lower surface of the PCB 11. The probe pins 13 may be supported by a support member 18. A pad 17 may be on an upper surface of the PCB 11 and may be electrically connected to a connection PCB (not shown in FIG. 1B).
If an EDS test is performed on a semiconductor wafer 20 using the related art probe card 10, a bonding pad (not shown) of a semiconductor chip of the semiconductor wafer 20 mounted on a wafer stage 21 may contact the probe pins 13 of the probe card 10. A test signal may be transmitted from a tester (not shown) to the semiconductor chip of the semiconductor wafer 20 through the probe card 10, and an electrical property signal may be transmitted from the semiconductor chip to the tester through the probe card 10. The tester may determine whether the semiconductor chip is defective based on the electrical property signal provided from the semiconductor chip.
A related art probe card may test one semiconductor chip at a time and may result in a high precision test. A related art probe card may require a long test time to test a plurality of semiconductor chips on a wafer. Yield and productivity may be reduced for a related art probe card test. A multi-type probe card may probe a plurality of semiconductor chips at a time and may reduce a test time and improve productivity. Precision of the multi-type probe card may be lower. Because the related art probe card may be expensive, cost for fabricating a semiconductor device may be increased.